Unknown Year, 5.2L MC68HC16Z2 Initialization Code Overview

• Reset Vector = 0x0

First byte of reset vector = PK (Program Counter Extension)

Second byte of reset vector = SK (Stack Pointer Extension)

Third byte of reset vector = ZK (Index Z Extension)

PK = 0x01

SK = 0xFF

ZK = 0xFF

Initial PC = 0x0 | PK = (0x10000)

• 0x10000 Jump to 0x20000

• 0x20002 Wrote 0xFF to SK

• 0x20004 Wrote 0xFF to ZK

• 0x20006 Wrote 0xF8FE to SP

• 0x2000A Wrote 0xF800 to Z

• 0x20010 Wrote 0x00 to EK, XK, & YK

• 0x2001E Write 0xB4 to SYPCR

Enabled Watchdog

Turned off scaling

Set timeout to 2 to the 15th

• 0x20024 Wrote 0x55 to SWSR

• 0x2002A Wrote 0xAA to SWSR

Writing 0x55 then 0xAA to SWSR pets the watchdog

• 0x20032 Wrote 0xFF to RAMBAH
• 0x2003A Wrote 0x8000 to RAMBAL

This set RAM to start at 0xF8000

• 0x2003E cleared RAMMCR

Took RAM out of low power mode and enabled it.

Allowed writes to RAM from IMB

• 0x2004C ORed 0x8100 to SIMCR

Turned off external clock

Set external bus master to have direct access to IMB

• 0x20052 Wrote 0x30 to PEPAR

Port E Pin Assignment

Set PEPA5 as Address Strobe

Set PEPA4 as Data Strobe

• 0x20056 Wrote 0x30 to DDRE

Port E Pin Direction

Set DDE5 & DDE4 as outputs

• 0x20062 Wrote 0x3FFF to CSPAR0
• 0x20066 wrote 0x0300 to CSPAR1

Set CS10 (ADR23)

• 0x20072 Wrote 0xFE02 to CSBARBT

Set boot rom chip select base address to:

0xFE0000 size 16k

• 0x20076 Wrote 0x6BB0 to CSORBT

Set Async chip select assertion

Set Upper and lower byte chip select

Set Chip select to assert only for a read

Set Chip select to assert synchronized with data strobe

Set DSACK fast termination

Set Chip select address space to Supervisor/User

Enabled all interrupt levels & external interrupt vector

• 0x20082 Wrote 0x0500 to CSBAR0

Set Chip select 0 base address to:

0x050000 size 2k

• 0x20084 Wrote 0x6870 to CSOR0

One wait state