Difference between revisions of "Unknown Year, 5.2L MC68HC16Z2 Initialization Code Overview"
From JTEC_PCM
(More initialization) |
(Even more initialization) |
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* 0x200E6 Wrote 0x0 to CSOR6 | * 0x200E6 Wrote 0x0 to CSOR6 | ||
:Chip select 6 disabled | :Chip select 6 disabled | ||
| + | |||
| + | |||
| + | * 0x200F2 Wrote 0xFFF8 to CSBAR7 | ||
| + | :Set Chip select 7 base address to: | ||
| + | 0xFF800 size 2K | ||
| + | |||
| + | * 0x200F6 Wrote 0x2801 to CSOR7 | ||
| + | :Lower byte only | ||
| + | :Read only | ||
| + | :No wait | ||
| + | :CPU space | ||
| + | :Any interrupt level | ||
| + | :Autovector enabled | ||
| + | |||
| + | |||
| + | * 0x20102 Wrote 0x0 to CSBAR8 | ||
| + | * 0x20106 Wrote 0x0 to CSOR8 | ||
| + | :Chip select 8 disabled | ||
| + | |||
| + | |||
| + | * 0x20112 Wrote 0x0 to CSBAR9 | ||
| + | * 0x20116 Wrote 0x0 to CSOR9 | ||
| + | :Chip select 9 disabled | ||
| + | |||
| + | |||
| + | * 0x20122 Wrote 0x0005 to CSBAR10 | ||
| + | :Set Chip select 10 base address to: | ||
| + | 0x0 size 256K | ||
| + | |||
| + | * 0x20126 Wrote 0x6830 to CSOR10 | ||
| + | :Upper and lower bytes | ||
| + | :Read only | ||
| + | :Address strobe | ||
| + | :No wait | ||
| + | :Supervisor / User space | ||
| + | :Any interrupt level | ||
| + | :External interrupt vector | ||
| + | |||
| + | |||
| + | * 0x20130 Wrote 0x0 to PFPAR | ||
| + | :Set all port F pins to I/O pins | ||
| + | |||
| + | |||
| + | * 0x20138 Wrote 0x0 to ADCMCR | ||
| + | :Set ADC to normal operation from low power mode | ||
| + | :Ignore IFREEZE signal | ||
| + | :Set to unrestricted access | ||
| + | |||
| + | * 0x20140 wrote 0xE3 to ADCTL0 | ||
| + | :Set to 10 bit resolution | ||
| + | :Set to 16 A/D clock periods | ||
| + | Set divisor to 8 (Max system clock is 16MHz, Min system clock is 4MHz) | ||
Revision as of 13:13, 2 March 2012
- Reset Vector = 0x0
- First byte of reset vector = PK (Program Counter Extension)
- Second byte of reset vector = SK (Stack Pointer Extension)
- Third byte of reset vector = ZK (Index Z Extension)
- PK = 0x01
- SK = 0xFF
- ZK = 0xFF
- Initial PC = 0x0 | PK = (0x10000)
- 0x10000 Jump to 0x20000
- 0x20002 Wrote 0xFF to SK
- 0x20004 Wrote 0xFF to ZK
- 0x20006 Wrote 0xF8FE to SP
- 0x2000A Wrote 0xF800 to Z
- 0x20010 Wrote 0x00 to EK, XK, & YK
- 0x2001E Write 0xB4 to SYPCR
- Enabled Watchdog
- Turned off scaling
- Set timeout to 2 to the 15th
- 0x20024 Wrote 0x55 to SWSR
- 0x2002A Wrote 0xAA to SWSR
- Writing 0x55 then 0xAA to SWSR pets the watchdog
- 0x20032 Wrote 0xFF to RAMBAH
- 0x2003A Wrote 0x8000 to RAMBAL
- This set RAM to start at 0xF8000
- 0x2003E cleared RAMMCR
- Took RAM out of low power mode and enabled it.
- Allowed writes to RAM from IMB
- 0x2004C ORed 0x8100 to SIMCR
- Turned off external clock
- Set external bus master to have direct access to IMB
- 0x20052 Wrote 0x30 to PEPAR
- Port E Pin Assignment
- Set PEPA5 as Address Strobe
- Set PEPA4 as Data Strobe
- 0x20056 Wrote 0x30 to DDRE
- Port E Pin Direction
- Set DDE5 & DDE4 as outputs
- 0x20062 Wrote 0x3FFF to CSPAR0
- 0x20066 wrote 0x0300 to CSPAR1
- Set CS10 (ADR23)
- 0x20072 Wrote 0xFE02 to CSBARBT
- Set boot rom chip select base address to:
- 0xFE0000 size 16K
- 0x20076 Wrote 0x6BB0 to CSORBT
- Set Async chip select assertion
- Set Upper and lower byte chip select
- Set Chip select to assert only for a read
- Set Chip select to assert synchronized with data strobe
- Set DSACK fast termination
- Set Chip select address space to Supervisor/User
- Enabled all interrupt levels & external interrupt vector
- 0x20082 Wrote 0x0500 to CSBAR0
- Set Chip select 0 base address to:
- 0x050000 size 2K
- 0x20084 Wrote 0x6870 to CSOR0
- One wait state
- 0x20092 Wrote 0x0005 to CSBAR1
- Set Chip select 1 base address to:
- 0x0 size 256K
- 0x20094 Wrote 0x5070 to CSOR1
- Upper byte only
- Write only
- Address strobe
- 1 Wait cycle
- Supervisor/User space
- 0x200A2 Wrote 0x0005 to CSBAR2
- Set Chip select 2 base address to:
- 0x0 size 256K
- 0x200A6 Wrote 0x3070 to CSOR2
- Lower byte only
- Write only
- Address strobe
- 1 Wait cycle
- Supervisor/User space
- 0x200B2 Wrote 0x0 to CSBAR3
- 0x200B6 Wrote 0x0 to CSOR3
- Chip select 3 disabled
- 0x200C2 Wrote 0x0 to CSBAR4
- 0x200C6 Wrote 0x0 to CSOR4
- Chip select 4 disabled
- 0x200D2 Wrote 0x0400 to CSBAR5
- Set Chip select 5 base address to:
- 0x40000 size 2K
- 0x200D6 Wrote 0x3070 to CSOR5
- Lower byte only
- Write only
- Address sstrobe
- 1 Wait cycle
- Supervisor/User space
- 0x200E2 Wrote 0x0 to CSBAR6
- 0x200E6 Wrote 0x0 to CSOR6
- Chip select 6 disabled
- 0x200F2 Wrote 0xFFF8 to CSBAR7
- Set Chip select 7 base address to:
0xFF800 size 2K
- 0x200F6 Wrote 0x2801 to CSOR7
- Lower byte only
- Read only
- No wait
- CPU space
- Any interrupt level
- Autovector enabled
- 0x20102 Wrote 0x0 to CSBAR8
- 0x20106 Wrote 0x0 to CSOR8
- Chip select 8 disabled
- 0x20112 Wrote 0x0 to CSBAR9
- 0x20116 Wrote 0x0 to CSOR9
- Chip select 9 disabled
- 0x20122 Wrote 0x0005 to CSBAR10
- Set Chip select 10 base address to:
0x0 size 256K
- 0x20126 Wrote 0x6830 to CSOR10
- Upper and lower bytes
- Read only
- Address strobe
- No wait
- Supervisor / User space
- Any interrupt level
- External interrupt vector
- 0x20130 Wrote 0x0 to PFPAR
- Set all port F pins to I/O pins
- 0x20138 Wrote 0x0 to ADCMCR
- Set ADC to normal operation from low power mode
- Ignore IFREEZE signal
- Set to unrestricted access
- 0x20140 wrote 0xE3 to ADCTL0
- Set to 10 bit resolution
- Set to 16 A/D clock periods
Set divisor to 8 (Max system clock is 16MHz, Min system clock is 4MHz)
